The basic structure and function of FPGA

Field-programmable gate array (FPGA) emerged in the mid 1980s a new kind of user-programmable devices, programmable logic devices and general different, FPGA's high integration, logic implementation ability, better design flexibility. The basic structure of FPGA programmable resources typically contains three types: a programmable logic block (CLB), programmable input and output blocks and programmable interconnect. Programmable logic function blocks (CLB) is a realization of the user's base unit, they are typically arranged in an array of regularly, distributed throughout the chip; Programmable logic output block to complete the on-chip interface to the external packaging of the leg, often around the array arranged in around the chip; programmable interconnect includes various lengths and the number of programmable segment connecting the connection switches, they will each programmable logic block, input and output blocks are connected together to form a specific function of the circuit.
As a result of the different switching elements, FPGA reflect different programmable features, some of which are one-time programmable, others are reprogrammable.Graphic LCD Module One-time-programmable FPGA using inverse fuse as switching elements, when the program ends with a reverse voltage fuse, the fuse will reverse from high impedance to low impedance in order to achieve the connection between the two points. After programming, the operating voltage even if the removal of such FPGA configuration data is retained. Since only be programmed once, so it is more suitable for styling products and high-volume applications. In addition, lcm module it is also commonly used in high performance and confidentiality requirements of the occasion. Reprogrammable FPGA SRAM-type switch or flash EPROM controlled switching elements. SRAM-type switching element comprises a transistor composed of a RAM, and five called PIP (programmable internal connection point) of the transistor. PIP control of each cabling channel connections, PIP and by their next of RAM unit control. RAM cell is stored PIP-off information, which code is the system is powered by the external written to the internal RAM in FPGA. Power is cut off, RAM data will be lost, so the use of the FPGA SRAM-type switch is volatile, and each time re-power, FPGA should be restructured. Outstanding advantages of SRAM-based FPGA is programmed repeatedly, the system is powered on, the FPGA loading different configuration data, you can make it perform different hardware capabilities. This configuration changes can even be running in the system, dynamic reconfiguration of system functions.