Protection circuit parasitic inductance

TVS diodes in the path parasitic inductance in an ESD event will produce severe voltage overshoot.COG LCD Display Despite the use of TVS diodes, due to the induced voltage across the inductive load VL = L × di / dt, the high voltage overshoot protection IC may still exceed the voltage threshold for damage. The total protection circuit withstand voltage TVS diode clamp voltage and the voltage of the parasitic inductance and, VT = VC + VL. An ESD transient induced current time in less than 1ns able to reach the peak (in accordance with IEC 61000-4-2 standard), assuming the lead inductance per inch 20nH, line length is a quarter-inch, overshoot voltage is 50V / 10A pulses.
Experience design criterion is designed to be as short as possible shunt pathway, thereby reducing the parasitic inductance effects.
All paths must be considered inductive ground loops, TVS and the protected path between the signal line, and a connector to the TVS device path. Protected signal line should be connected directly to the ground, without a ground plane, the ground loop connections should be as short as possible. TVS diode protection circuit ground and the distance between the ground should be as short as possible to minimize parasitic inductance ground plane. Finally, TVS device should be placed as close as possible to minimize the connector into the adjacent line transient coupling.lcm module Although there is no direct path to the connector, but this secondary radiation effect will lead to other parts of the work board disorder.